Editor, Author at Institute of Nano Electronic Engineering

Anbar University Lecturers Join Nanomaterial Technology Short Course

October 31, 2012 By Editor

Anbar University Lecturers Join Nanomaterial Technology Short Course
Institute of Nano Electronic Engineering (INEE) has organized a short course for nine lecturers from the University of Anbar, Iraq in the field of nanomaterial technology on 15 to 25 October 2012 ago.

Whole course took about nine days, where the theory held in the morning, while the practical side of the lab INEE held in the afternoon. In theory, the participant was revealed in all aspects of nanomaterial technology that covers the mathematical model, the basic theory of materials, materials synthesis, physical and electrical characterization methods. Facility design basis for clean rooms and other critical facility in the field of nanotechnology fabrication is also presented.

In the practical aspect, participants exposed to the fabrication technology of nano as photolithography, etching, oxidation, metallization and the like.

Overall, participants very satisfied with the course conducted and admitted that many things have been learned. They also praised the progress that has been achieved by UniMAP in particular, and Malaysia in general.

INEE are expected to hold the same course to the second group of Anbar University in November 2012.

Anbar University Lecturers Join Nanomaterial Technology Short Course

Prepared by:
Ramzan Mat Ayub
Deputy Director
ramzan@unimap.edu.my

Download report: Anbar University Nanomateril Technology Short Course Report (Malay)

Fabrication and Characterization of 50 nm Silicon Nano-Gap Structures

October 24, 2012 By Editor

Abstract – A simple method for the fabrication of nano-gaps less than 50 nm by using conventional photolithography combined with patterned-size reduction techniques is presented. Silicon material is used to fabricate the nano-gap structure and gold is used for the electrode. Two chrome masks are proposed to complete this work, the first mask for the nano-gap pattern and a second mask for the electrode. The method is based on the control of the coefficients (temperature and time) with an improved pattern size resolution by thermal oxidation. With this technique, there are no principal limitations to fabricating anostructures with different layouts down to several nanometers in dimension. In this work, the proposed method is experimentally demonstrated by preparing the nano-gaps on a Si–SiO2 substrate down to dimensions of 50 nm. The optical characterization that is applied to check the nano-gap structure is by using the scanning electron microscope (SEM).

Keywords – Nano-Gap, Pattern-Size Reduction, Nanostructure, Optical Characterization, Photolithography.

Corresponding Author: Uda Hashim
Corresponding Author’s Email: uda@unimap.edu.my

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Carbon nano dots scale by focused ion beam system for MIS diode nano devices

October 3, 2012 By Editor

Abstract – Metal-insulator-semiconductor (MIS) structures with a nanocrystal carbon (nc-C) embedded in SiO2 thin films were fabricated using a focused ion beam (FIB) system with a precursor of low-energy Ga+ ion and carbon source. The crystallinity of nc-C was investigated by Raman spectroscopy and atomic force microscopy (AFM). Raman spectra indicate the evidence of crystallization of nc-C after annealed at 600˚C by the sharp peak at 1565 cm-1 in graphite (sp2), while no peak of diamond (sp3) could be seen at 1333 cm-1. The AFM images showed the nc-C dots controlled with diameter of 100 nm, 200 nm and 300 nm, respectively. The above results revealed that the nc-C dots had sufficiently stuck onto SiO2 films. The hysterisis loop in the capacitance–voltage characteristics appeared in the MIS device with SiO2/nc-C/SiO2 structure in which voltage shift is 0.32 V for radical oxidation and 0.14 V for dry oxidation, respectively.

Keywords – Carbon; Nanocrystal; Memory device; Focused ion beam; Raman spectroscopy; Atomic force microscopy

Corresponding Author: Ruslinda Abdul Rahim
Corresponding Author’s Email: ruslinda@unimap.edu.my

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The Alignment of Carbon Nano Tube between Aluminum Electrodes using AC Dielectrophoresis Method

September 26, 2012 By Editor

Abstract – This paper presents the recent development and fabrication of carbon nanotubes (CNT) based on electrical devices. The silicon oxide is formed by dry oxidation and the Aluminum (Al) layer is deposited using Thermal Evaporator. The electrodes pad act as a bridge for CNT alignment. Then, this single-walled carbon nanotubes (SWNTs) was suspended in isopropyl alcohol (IPA) and Dichloromethane (DCM) solution in ultrasonic condition around 1 hour continuously. Then, the aligment of the CNT was carried out using AC dielectrophoresis and DC electrophoresis method.

Keywords – CNT, DC electrophoresis method, AC dielectrophoresis method

Corresponding Author: Nur Hamidah Abdul Halim
Corresponding Author’s Email: nurhamidah@unimap.edu.my

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Fabrication and characterization of ONO and tunnel oxide for 16k FLOTOX EEPROM cell

September 25, 2012 By Editor

Abstract – The EEPROM process is one the hardest process to be developed. The performance of the EEPROM devices is normally judged on the programming speed, which relates to program high (erase) and program low (write) operations. It is essential that the program high and program low speed of the EEPROM cell is within 1ms with a programming voltage of not more than 16V. In this study, two experiments were setup to improve the programming speed. The first experiment was to increase the high voltage NMOS drain junction breakdown voltage with the source floating (HVNMOS BVDSF), and the second experiment was to scale down the ONO layer. The characterization work to increase the programming speed of the memory cell of 16k FLOTOX EEPROM has been carried out. P-field implant dose is optimized to have both the HVNMOS BVDSF and the p-field threshold voltage above 16V for fast programming. As a result, the threshold voltages of programming high and low operation are achieved at 4.35V and .0.77V respectively. Furthermore, by scaling down the nitride layer of ONO from 160Å to 130Å, the Vt program window is further improved to 4.5V and .0.94V for the program high and program low operations respectively.

Keywords – EEPROM, memory cell, threshold voltage, program high, program low, ONO, nitride layer.

Corresponding Author: R.M. Ayub
Corresponding Author’s Email: ramzan@unimap.edu.my

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